1. Field of the Invention
The present invention generally relates to the field of semiconductor structures and processes. More particularly, the invention relates to planarization methods and structures used in semiconductor processing.
2. Background Art
Liquid Crystal on Silicon (LCoS) devices can be utilized to create high-resolution images in electronic devices, such as televisions and other types of displays. In a television, for example, a separate LCoS device is required for each color (blue, green, and red). Each LCoS device can include a liquid crystal, which includes polarizing layers of liquid crystal molecules, overlying an array of pixel electrodes, which can be formed in a top metal layer of a semiconductor structure. In the LCoS device, a voltage can be applied to each pixel electrode to control an amount of light passing through an overlying portion of the liquid crystal. To achieve effective operation, the pixel electrodes in the semiconductor structure typically include a highly reflective metal, such as aluminum. For proper integration and alignment with the liquid crystal, the semiconductor structure underlying the liquid crystal requires a passivation layer with a substantially planar top surface.
Conventionally, substantially planar passivation layer overlying the pixel electrodes in the semiconductor structure can be provided by depositing an interlayer dielectric over the pixel electrodes and in the gaps between adjacent pixel electrodes. The interlayer dielectric can be planarized by utilizing a suitable planarizing process, such as a chemical mechanical polishing (CMP) process, followed by an etch back process to expose the top surfaces of the pixel electrodes. An Oxide-Nitride-Oxide (ONO) stack can then be formed over the pixel electrodes and the dielectric material remaining in the gaps between the adjacent pixel electrodes to provide a passivation layer having a substantially planar top surface. However, to achieve a substantially planar passivation layer overlying the pixel electrodes in the semiconductor structure, the conventional approach requires planarization and etch back steps, which are undesirably complicated to perform.